HashinIsraq
// Design Verification Engineer @ Ulkasemi
// Tech Enthusiast
Bridging silicon and software - verifying digital ICs with UVM & SystemVerilog by day, crafting modern web experiences with Full Stack Web Development, Artificial Intelligence & Cyber Security by night.
Who I Am
Hello! I'm Hashin Israq, a Design Verification Engineer at Ulkasemi Pvt. Ltd based in Dhaka, Bangladesh.
I am deeply interested in VLSI, Nanotechnology, Problem Solving, and Software Development. I take great pride in my work and continuously learn new technologies and tools to enrich my knowledge and skills.
I bridge the gap between hardware and software - verifying complex digital designs at the silicon level while crafting modern technologies on the web. I am passionate about creating efficient, scalable, and user-friendly solutions that make a positive impact on people's lives.
My Toolkit
Selected Projects
LPDDR5X DDR5 PHY PHYINIT QUALIFICATION
PHYINIT qualification for a LPDDR5X DDR5 memory PHY. Verified firmware-driven initialization and training sequences (PLL init, ZQ calibration, read/write leveling, DQ training) across DFI-compliant configurations, debugging training failures down to waveform and log level in a UVM environment.
DDR5 MRPHY PHYINIT QUALIFICATION
PHYINIT qualification for a DDR5 memory PHY. Verified firmware-driven initialization and training sequences (PLL init, ZQ calibration, read/write leveling, DQ training) across DFI-compliant configurations, debugging training failures down to waveform and log level in a UVM environment.
DDR54 PHYINIT QUALIFICATION
Qualified PHYINIT flows for a combo DDR5/DDR4 PHY across multiple protocol modes and speed grades. Validated initialization, mode register configuration, and training step coverage against the DFI spec, isolating and root-causing simulation failures across regression suites.
DDR5 MRPHY GEN2 GLS
Gate-level simulation and verification of DDR5 memory PHY using UVM methodology. Involved complex DFI interface verification and advanced debug workflows.
AXI Protocol Verification
Functional verification of AXI high-performance bus protocol using a complete UVM testbench with assertions, coverage, and bug reporting.
AHB Protocol Verification
Full UVM-based functional verification of AHB bus protocol, covering all transfer types with comprehensive coverage metrics.
I2C Protocol Verification
I2C protocol verification with UVM testbench, covering master/slave modes, clock stretching, and multi-master arbitration.
SPI Protocol Verification
SPI four-wire serial communication protocol verification using SystemVerilog UVM with full assertion and functional coverage.
APB Protocol Verification
APB peripheral bus protocol testbench using UVM methodology with coverage-driven verification and bug reporting.
Universal Shift Register
Functional verification of a Universal Shift Register using SystemVerilog and UVM testbench with full assertions and coverage.
SoC Design: Smart Elevator
Complete System-on-Chip design of a Smart Elevator controller, from RTL design through synthesis and physical implementation using Cadence toolchain.
AUST PIC Website
Full-stack development of AUST Programming and Informatics Club website with React.js, MongoDB, and Material-UI, designed in Figma.
Single Phase Sine Wave Inverter
Designed and implemented a single phase sine wave inverter using Arduino with hardware installation and SPWM techniques.
2-bit Magnitude Comparator
High performance 2-bit magnitude comparator using hybrid logic style in Cadence Virtuoso, with full DRC and LVS verification.
Detection System: Radar
Arduino-based radar detection system with real-time visualization using Processing App and ultrasonic sensor.
PI Controller (MATLAB)
PI controller simulation in MATLAB Simulink with hardware implementation and real-time performance evaluation.
Variable Frequency Drive
Cost-effective Variable Frequency Drive hardware design and implementation for motor speed control applications.
FDM System for DSB AM Audio (MATLAB)
Design of a simple FDM system for DSB AM audio signal using MATLAB - modulation, multiplexing, and signal analysis.
Load Flow Studies
Load flow analysis and power system studies using PowerWorld Simulator for a multi-bus power network.
AutoCAD Home Design
Detailed 2D home floor plan and electrical layout designed using AutoCAD Electrical.
Temperature Controlled DC Fan
Hardware implementation of a temperature-controlled DC fan using thermistor and transistor-based speed control.
Certifications & Training
Published Work
SCAPS Numerical Design of MoSe₂ Solar Cell for Different Buffer Layers
Research on the SCAPS numerical design of MoSe₂ solar cells with different buffer layers, published in Chalcogenide Letters. The findings provide valuable insights for optimizing solar cell design and enhancing energy conversion efficiency, contributing to advancements in thin-film photovoltaic technology.
Community Involvement
AUST Programming and Informatics Club (PIC)
- →Developed the club's official website using React.js
- →Organized and managed club events as an organizer
IEEE AUST Student Branch (IASB)
- →Organized technical events as a volunteer
AUST Innovation and Design Club (IDC)
- →Organized innovation and design events as a volunteer
TGBHS Bangladesh National Cadet Corps (BNCC)
- →Completed a Capsule Camp in Dinajpur Government College
Let's Connect
Whether it's a design verification challenge, a web development project, cyber security project or just a conversation about VLSI and technology - I'm always open to interesting opportunities.